//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
.global .texref texture2_2D;
// ShaderKernel_PrColorToneCurves$__cuda_local_var_180684_588_non_const_p_local has been demoted

.visible .entry ShaderKernel_PrColorToneCurves(
	.param .u64 ShaderKernel_PrColorToneCurves_param_0,
	.param .u32 ShaderKernel_PrColorToneCurves_param_1,
	.param .u32 ShaderKernel_PrColorToneCurves_param_2,
	.param .u32 ShaderKernel_PrColorToneCurves_param_3,
	.param .u32 ShaderKernel_PrColorToneCurves_param_4,
	.param .u64 ShaderKernel_PrColorToneCurves_param_5,
	.param .u64 ShaderKernel_PrColorToneCurves_param_6,
	.param .u64 ShaderKernel_PrColorToneCurves_param_7,
	.param .u64 ShaderKernel_PrColorToneCurves_param_8
)
{
	.reg .pred 	%p<26>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<25>;
	.reg .f32 	%f<170>;
	.reg .s64 	%rd<27>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_PrColorToneCurves$__cuda_local_var_180684_588_non_const_p_local[16];

	ld.param.u64 	%rd3, [ShaderKernel_PrColorToneCurves_param_0];
	ld.param.u32 	%r5, [ShaderKernel_PrColorToneCurves_param_1];
	ld.param.u32 	%r6, [ShaderKernel_PrColorToneCurves_param_2];
	ld.param.u32 	%r7, [ShaderKernel_PrColorToneCurves_param_3];
	ld.param.u32 	%r8, [ShaderKernel_PrColorToneCurves_param_4];
	ld.param.u64 	%rd4, [ShaderKernel_PrColorToneCurves_param_5];
	ld.param.u64 	%rd5, [ShaderKernel_PrColorToneCurves_param_8];
	mov.u32 	%r9, %ntid.x;
	mov.u32 	%r10, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r9, %r10, %r1;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r3, %r11, %r12, %r13;
	setp.lt.s32	%p1, %r2, %r7;
	setp.lt.s32	%p2, %r3, %r8;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_28;
	bra.uni 	BB0_1;

BB0_1:
	setp.ne.s32	%p4, %r1, 0;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd6, %rd4;
	ld.global.v4.f32 	{%f41, %f42, %f43, %f44}, [%rd6];
	st.shared.v4.f32 	[ShaderKernel_PrColorToneCurves$__cuda_local_var_180684_588_non_const_p_local], {%f41, %f42, %f43, %f44};

BB0_3:
	cvta.to.global.u64 	%rd1, %rd5;
	cvt.rn.f32.s32	%f49, %r2;
	add.ftz.f32 	%f1, %f49, 0f3F000000;
	cvt.rn.f32.s32	%f50, %r3;
	add.ftz.f32 	%f2, %f50, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f51, %f52, %f53, %f54}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	ld.global.u32 	%r4, [%rd1];
	setp.eq.s32	%p5, %r4, 0;
	ld.shared.f32 	%f57, [ShaderKernel_PrColorToneCurves$__cuda_local_var_180684_588_non_const_p_local];
	mul.ftz.f32 	%f58, %f53, %f57;
	mul.ftz.f32 	%f59, %f52, %f57;
	mul.ftz.f32 	%f60, %f51, %f57;
	selp.f32	%f7, %f53, %f58, %p5;
	selp.f32	%f8, %f52, %f59, %p5;
	selp.f32	%f9, %f51, %f60, %p5;
	cvt.ftz.sat.f32.f32	%f10, %f7;
	cvt.ftz.sat.f32.f32	%f11, %f8;
	cvt.ftz.sat.f32.f32	%f12, %f9;
	ld.global.u32 	%r14, [%rd1+4];
	setp.eq.s32	%p6, %r14, 0;
	mov.f32 	%f163, %f10;
	mov.f32 	%f166, %f11;
	mov.f32 	%f169, %f12;
	@%p6 bra 	BB0_14;

	setp.gtu.ftz.f32	%p7, %f10, 0f00000000;
	@%p7 bra 	BB0_6;

	mov.f32 	%f155, 0f3A000000;
	bra.uni 	BB0_7;

BB0_6:
	lg2.approx.ftz.f32 	%f62, %f10;
	mul.ftz.f32 	%f63, %f62, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f64, %f63;
	fma.rn.ftz.f32 	%f155, %f64, 0f3F7FF000, 0f3A000000;

BB0_7:
	setp.gtu.ftz.f32	%p8, %f11, 0f00000000;
	@%p8 bra 	BB0_9;

	mov.f32 	%f156, 0f3A000000;
	bra.uni 	BB0_10;

BB0_9:
	lg2.approx.ftz.f32 	%f66, %f11;
	mul.ftz.f32 	%f67, %f66, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f68, %f67;
	fma.rn.ftz.f32 	%f156, %f68, 0f3F7FF000, 0f3A000000;

BB0_10:
	setp.gtu.ftz.f32	%p9, %f12, 0f00000000;
	@%p9 bra 	BB0_12;

	mov.f32 	%f157, 0f3A000000;
	bra.uni 	BB0_13;

BB0_12:
	lg2.approx.ftz.f32 	%f70, %f12;
	mul.ftz.f32 	%f71, %f70, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f72, %f71;
	fma.rn.ftz.f32 	%f157, %f72, 0f3F7FF000, 0f3A000000;

BB0_13:
	mov.f32 	%f90, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f73, %f74, %f75, %f76}, [texture2_2D, {%f155, %f90}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f79, %f80, %f81, %f82}, [texture2_2D, {%f156, %f90}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f85, %f86, %f87, %f88}, [texture2_2D, {%f157, %f90}];
	// inline asm
	setp.gt.ftz.f32	%p10, %f76, %f82;
	selp.f32	%f91, %f82, %f76, %p10;
	setp.gt.ftz.f32	%p11, %f91, %f88;
	selp.f32	%f92, %f88, %f91, %p11;
	selp.f32	%f93, %f76, %f82, %p10;
	setp.gt.ftz.f32	%p12, %f93, %f88;
	selp.f32	%f94, %f93, %f88, %p12;
	setp.gt.ftz.f32	%p13, %f10, %f11;
	selp.f32	%f95, %f10, %f11, %p13;
	setp.gt.ftz.f32	%p14, %f95, %f12;
	selp.f32	%f96, %f95, %f12, %p14;
	selp.f32	%f97, %f11, %f10, %p13;
	setp.gt.ftz.f32	%p15, %f97, %f12;
	selp.f32	%f98, %f12, %f97, %p15;
	sub.ftz.f32 	%f99, %f96, %f98;
	sub.ftz.f32 	%f100, %f94, %f92;
	setp.gt.ftz.f32	%p16, %f99, 0f2EDBE6FF;
	selp.f32	%f101, %f99, 0f2EDBE6FF, %p16;
	mov.f32 	%f102, 0f3F800000;
	div.rn.ftz.f32 	%f103, %f102, %f101;
	mul.ftz.f32 	%f104, %f103, %f100;
	sub.ftz.f32 	%f105, %f10, %f98;
	sub.ftz.f32 	%f106, %f11, %f98;
	sub.ftz.f32 	%f107, %f12, %f98;
	fma.rn.ftz.f32 	%f19, %f104, %f105, %f92;
	fma.rn.ftz.f32 	%f20, %f104, %f106, %f92;
	fma.rn.ftz.f32 	%f21, %f104, %f107, %f92;
	mov.f32 	%f163, %f19;
	mov.f32 	%f166, %f20;
	mov.f32 	%f169, %f21;

BB0_14:
	mov.f32 	%f167, %f169;
	mov.f32 	%f168, %f167;
	mov.f32 	%f164, %f166;
	mov.f32 	%f165, %f164;
	mov.f32 	%f161, %f163;
	mov.f32 	%f162, %f161;
	ld.global.u32 	%r15, [%rd1+8];
	setp.eq.s32	%p17, %r15, 0;
	@%p17 bra 	BB0_25;

	setp.gtu.ftz.f32	%p18, %f162, 0f00000000;
	@%p18 bra 	BB0_17;

	mov.f32 	%f158, 0f3A000000;
	bra.uni 	BB0_18;

BB0_17:
	lg2.approx.ftz.f32 	%f109, %f162;
	mul.ftz.f32 	%f110, %f109, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f111, %f110;
	fma.rn.ftz.f32 	%f158, %f111, 0f3F7FF000, 0f3A000000;

BB0_18:
	setp.gtu.ftz.f32	%p19, %f165, 0f00000000;
	@%p19 bra 	BB0_20;

	mov.f32 	%f159, 0f3A000000;
	bra.uni 	BB0_21;

BB0_20:
	lg2.approx.ftz.f32 	%f113, %f165;
	mul.ftz.f32 	%f114, %f113, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f115, %f114;
	fma.rn.ftz.f32 	%f159, %f115, 0f3F7FF000, 0f3A000000;

BB0_21:
	setp.gtu.ftz.f32	%p20, %f168, 0f00000000;
	@%p20 bra 	BB0_23;

	mov.f32 	%f160, 0f3A000000;
	bra.uni 	BB0_24;

BB0_23:
	lg2.approx.ftz.f32 	%f117, %f168;
	mul.ftz.f32 	%f118, %f117, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f119, %f118;
	fma.rn.ftz.f32 	%f160, %f119, 0f3F7FF000, 0f3A000000;

BB0_24:
	mov.f32 	%f137, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f120, %f121, %f122, %f123}, [texture2_2D, {%f158, %f137}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f126, %f127, %f128, %f129}, [texture2_2D, {%f159, %f137}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f132, %f133, %f134, %f135}, [texture2_2D, {%f160, %f137}];
	// inline asm
	mov.f32 	%f168, %f134;
	mov.f32 	%f165, %f127;
	mov.f32 	%f162, %f120;

BB0_25:
	sub.ftz.f32 	%f138, %f7, %f10;
	sub.ftz.f32 	%f139, %f8, %f11;
	sub.ftz.f32 	%f140, %f9, %f12;
	mov.f32 	%f141, 0f3F800000;
	sub.ftz.f32 	%f142, %f141, %f162;
	setp.lt.ftz.f32	%p21, %f7, 0f00000000;
	selp.f32	%f143, %f142, %f162, %p21;
	fma.rn.ftz.f32 	%f144, %f138, %f143, %f162;
	sub.ftz.f32 	%f145, %f141, %f165;
	setp.lt.ftz.f32	%p22, %f8, 0f00000000;
	selp.f32	%f146, %f145, %f165, %p22;
	fma.rn.ftz.f32 	%f147, %f139, %f146, %f165;
	sub.ftz.f32 	%f148, %f141, %f168;
	setp.lt.ftz.f32	%p23, %f9, 0f00000000;
	selp.f32	%f149, %f148, %f168, %p23;
	fma.rn.ftz.f32 	%f150, %f140, %f149, %f168;
	ld.shared.f32 	%f151, [ShaderKernel_PrColorToneCurves$__cuda_local_var_180684_588_non_const_p_local+4];
	mul.ftz.f32 	%f152, %f144, %f151;
	mul.ftz.f32 	%f153, %f147, %f151;
	mul.ftz.f32 	%f154, %f150, %f151;
	selp.f32	%f38, %f144, %f152, %p5;
	selp.f32	%f39, %f147, %f153, %p5;
	selp.f32	%f40, %f150, %f154, %p5;
	mad.lo.s32 	%r24, %r3, %r5, %r2;
	cvt.s64.s32	%rd2, %r24;
	setp.eq.s32	%p25, %r6, 0;
	@%p25 bra 	BB0_27;

	cvta.to.global.u64 	%rd21, %rd3;
	shl.b64 	%rd22, %rd2, 4;
	add.s64 	%rd23, %rd21, %rd22;
	st.global.v4.f32 	[%rd23], {%f40, %f39, %f38, %f54};
	bra.uni 	BB0_28;

BB0_27:
	cvta.to.global.u64 	%rd24, %rd3;
	shl.b64 	%rd25, %rd2, 3;
	add.s64 	%rd26, %rd24, %rd25;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f54;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f38;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f39;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f40;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd26], {%rs4, %rs3, %rs2, %rs1};

BB0_28:
	ret;
}


