//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
.global .texref texture2_2D;

.visible .entry ShaderKernel_Wheels(
	.param .u64 ShaderKernel_Wheels_param_0,
	.param .u32 ShaderKernel_Wheels_param_1,
	.param .u32 ShaderKernel_Wheels_param_2,
	.param .u32 ShaderKernel_Wheels_param_3,
	.param .u32 ShaderKernel_Wheels_param_4,
	.param .u64 ShaderKernel_Wheels_param_5,
	.param .u64 ShaderKernel_Wheels_param_6,
	.param .u64 ShaderKernel_Wheels_param_7
)
{
	.reg .pred 	%p<11>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<71>;
	.reg .s64 	%rd<16>;


	ld.param.u64 	%rd2, [ShaderKernel_Wheels_param_0];
	ld.param.u32 	%r3, [ShaderKernel_Wheels_param_1];
	ld.param.u32 	%r4, [ShaderKernel_Wheels_param_2];
	ld.param.u32 	%r5, [ShaderKernel_Wheels_param_3];
	ld.param.u32 	%r6, [ShaderKernel_Wheels_param_4];
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r1, %r5;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_13;
	bra.uni 	BB0_1;

BB0_1:
	cvt.rn.f32.s32	%f29, %r1;
	add.ftz.f32 	%f27, %f29, 0f3F000000;
	cvt.rn.f32.s32	%f30, %r2;
	add.ftz.f32 	%f28, %f30, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f23, %f24, %f25, %f26}, [texture0_RECT, {%f27, %f28}];
	// inline asm
	abs.ftz.f32 	%f5, %f25;
	abs.ftz.f32 	%f6, %f24;
	abs.ftz.f32 	%f7, %f23;
	abs.ftz.f32 	%f8, %f26;
	cvt.ftz.sat.f32.f32	%f9, %f5;
	cvt.ftz.sat.f32.f32	%f10, %f6;
	cvt.ftz.sat.f32.f32	%f11, %f7;
	setp.gtu.ftz.f32	%p4, %f9, 0f00000000;
	@%p4 bra 	BB0_3;

	mov.f32 	%f68, 0f3A000000;
	bra.uni 	BB0_4;

BB0_3:
	lg2.approx.ftz.f32 	%f32, %f9;
	mul.ftz.f32 	%f33, %f32, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f34, %f33;
	fma.rn.ftz.f32 	%f68, %f34, 0f3F7FF000, 0f3A000000;

BB0_4:
	sub.ftz.f32 	%f14, %f5, %f9;
	setp.gtu.ftz.f32	%p5, %f10, 0f00000000;
	@%p5 bra 	BB0_6;

	mov.f32 	%f69, 0f3A000000;
	bra.uni 	BB0_7;

BB0_6:
	lg2.approx.ftz.f32 	%f36, %f10;
	mul.ftz.f32 	%f37, %f36, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f38, %f37;
	fma.rn.ftz.f32 	%f69, %f38, 0f3F7FF000, 0f3A000000;

BB0_7:
	sub.ftz.f32 	%f17, %f6, %f10;
	setp.gtu.ftz.f32	%p6, %f11, 0f00000000;
	@%p6 bra 	BB0_9;

	mov.f32 	%f70, 0f3A000000;
	bra.uni 	BB0_10;

BB0_9:
	lg2.approx.ftz.f32 	%f40, %f11;
	mul.ftz.f32 	%f41, %f40, 0f3EE8BA2F;
	ex2.approx.ftz.f32 	%f42, %f41;
	fma.rn.ftz.f32 	%f70, %f42, 0f3F7FF000, 0f3A000000;

BB0_10:
	sub.ftz.f32 	%f61, %f7, %f11;
	fma.rn.ftz.f32 	%f48, %f8, 0f00000000, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f43, %f44, %f45, %f46}, [texture2_2D, {%f68, %f48}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f49, %f50, %f51, %f52}, [texture2_2D, {%f69, %f48}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f55, %f56, %f57, %f58}, [texture2_2D, {%f70, %f48}];
	// inline asm
	fma.rn.ftz.f32 	%f62, %f14, %f43, %f43;
	fma.rn.ftz.f32 	%f63, %f17, %f50, %f50;
	fma.rn.ftz.f32 	%f64, %f61, %f57, %f57;
	setp.lt.ftz.f32	%p7, %f25, 0f00000000;
	selp.f32	%f65, 0fBF800000, 0f3F800000, %p7;
	mul.ftz.f32 	%f20, %f62, %f65;
	setp.lt.ftz.f32	%p8, %f24, 0f00000000;
	selp.f32	%f66, 0fBF800000, 0f3F800000, %p8;
	mul.ftz.f32 	%f21, %f63, %f66;
	setp.lt.ftz.f32	%p9, %f23, 0f00000000;
	selp.f32	%f67, 0fBF800000, 0f3F800000, %p9;
	mul.ftz.f32 	%f22, %f64, %f67;
	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32	%rd1, %r13;
	setp.eq.s32	%p10, %r4, 0;
	@%p10 bra 	BB0_12;

	cvta.to.global.u64 	%rd10, %rd2;
	shl.b64 	%rd11, %rd1, 4;
	add.s64 	%rd12, %rd10, %rd11;
	st.global.v4.f32 	[%rd12], {%f22, %f21, %f20, %f26};
	bra.uni 	BB0_13;

BB0_12:
	cvta.to.global.u64 	%rd13, %rd2;
	shl.b64 	%rd14, %rd1, 3;
	add.s64 	%rd15, %rd13, %rd14;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f21;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f22;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f26;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd15], {%rs3, %rs2, %rs1, %rs4};

BB0_13:
	ret;
}


