//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;

.visible .entry ShaderKernel_Rec709toPQ(
	.param .u64 ShaderKernel_Rec709toPQ_param_0,
	.param .u32 ShaderKernel_Rec709toPQ_param_1,
	.param .u32 ShaderKernel_Rec709toPQ_param_2,
	.param .u32 ShaderKernel_Rec709toPQ_param_3,
	.param .u32 ShaderKernel_Rec709toPQ_param_4,
	.param .u64 ShaderKernel_Rec709toPQ_param_5,
	.param .u64 ShaderKernel_Rec709toPQ_param_6
)
{
	.reg .pred 	%p<23>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<22>;
	.reg .f32 	%f<122>;
	.reg .s64 	%rd<10>;


	ld.param.u64 	%rd2, [ShaderKernel_Rec709toPQ_param_0];
	ld.param.u32 	%r3, [ShaderKernel_Rec709toPQ_param_1];
	ld.param.u32 	%r4, [ShaderKernel_Rec709toPQ_param_2];
	ld.param.u32 	%r5, [ShaderKernel_Rec709toPQ_param_3];
	ld.param.u32 	%r6, [ShaderKernel_Rec709toPQ_param_4];
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r1, %r5;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_31;
	bra.uni 	BB0_1;

BB0_1:
	cvt.rn.f32.s32	%f47, %r1;
	add.ftz.f32 	%f45, %f47, 0f3F000000;
	cvt.rn.f32.s32	%f48, %r2;
	add.ftz.f32 	%f46, %f48, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f41, %f42, %f43, %f44}, [texture0_RECT, {%f45, %f46}];
	// inline asm
	abs.ftz.f32 	%f5, %f43;
	abs.ftz.f32 	%f6, %f42;
	abs.ftz.f32 	%f7, %f41;
	add.ftz.f32 	%f49, %f5, 0f3DCAC083;
	add.ftz.f32 	%f50, %f6, 0f3DCAC083;
	add.ftz.f32 	%f51, %f7, 0f3DCAC083;
	mul.ftz.f32 	%f8, %f49, 0f3F68F065;
	mul.ftz.f32 	%f9, %f50, 0f3F68F065;
	mul.ftz.f32 	%f10, %f51, 0f3F68F065;
	setp.gtu.ftz.f32	%p4, %f8, 0f00000000;
	@%p4 bra 	BB0_3;

	mov.f32 	%f113, 0f00000000;
	bra.uni 	BB0_4;

BB0_3:
	lg2.approx.ftz.f32 	%f53, %f8;
	mul.ftz.f32 	%f54, %f53, 0f400E38E4;
	ex2.approx.ftz.f32 	%f113, %f54;

BB0_4:
	setp.gtu.ftz.f32	%p5, %f9, 0f00000000;
	@%p5 bra 	BB0_6;

	mov.f32 	%f114, 0f00000000;
	bra.uni 	BB0_7;

BB0_6:
	lg2.approx.ftz.f32 	%f56, %f9;
	mul.ftz.f32 	%f57, %f56, 0f400E38E4;
	ex2.approx.ftz.f32 	%f114, %f57;

BB0_7:
	setp.gtu.ftz.f32	%p6, %f10, 0f00000000;
	@%p6 bra 	BB0_9;

	mov.f32 	%f115, 0f00000000;
	bra.uni 	BB0_10;

BB0_9:
	lg2.approx.ftz.f32 	%f59, %f10;
	mul.ftz.f32 	%f60, %f59, 0f400E38E4;
	ex2.approx.ftz.f32 	%f115, %f60;

BB0_10:
	add.ftz.f32 	%f61, %f5, 0fBDA5E354;
	add.ftz.f32 	%f62, %f6, 0fBDA5E354;
	add.ftz.f32 	%f63, %f7, 0fBDA5E354;
	mul.ftz.f32 	%f64, %f5, 0f3E638E39;
	mul.ftz.f32 	%f65, %f6, 0f3E638E39;
	mul.ftz.f32 	%f66, %f7, 0f3E638E39;
	setp.lt.ftz.f32	%p7, %f61, 0f00000000;
	selp.f32	%f67, %f64, %f113, %p7;
	setp.lt.ftz.f32	%p8, %f62, 0f00000000;
	selp.f32	%f68, %f65, %f114, %p8;
	setp.lt.ftz.f32	%p9, %f63, 0f00000000;
	selp.f32	%f69, %f66, %f115, %p9;
	setp.lt.ftz.f32	%p10, %f43, 0f00000000;
	selp.f32	%f70, 0fBC23D70A, 0f3C23D70A, %p10;
	mul.ftz.f32 	%f71, %f67, %f70;
	setp.lt.ftz.f32	%p11, %f42, 0f00000000;
	selp.f32	%f72, 0fBC23D70A, 0f3C23D70A, %p11;
	mul.ftz.f32 	%f73, %f68, %f72;
	setp.lt.ftz.f32	%p12, %f41, 0f00000000;
	selp.f32	%f74, 0fBC23D70A, 0f3C23D70A, %p12;
	mul.ftz.f32 	%f75, %f69, %f74;
	mul.ftz.f32 	%f76, %f73, 0f3E35CDD5;
	fma.rn.ftz.f32 	%f77, %f71, 0f3F528C8B, %f76;
	fma.rn.ftz.f32 	%f17, %f75, 0f00000000, %f77;
	mul.ftz.f32 	%f78, %f73, 0f3F7780AA;
	fma.rn.ftz.f32 	%f79, %f71, 0f3D07F598, %f78;
	fma.rn.ftz.f32 	%f18, %f75, 0fB456BF95, %f79;
	mul.ftz.f32 	%f80, %f73, 0f3D944B97;
	fma.rn.ftz.f32 	%f81, %f71, 0f3C8BF5D8, %f80;
	fma.rn.ftz.f32 	%f19, %f75, 0f3F6916DB, %f81;
	abs.ftz.f32 	%f20, %f17;
	abs.ftz.f32 	%f21, %f18;
	abs.ftz.f32 	%f22, %f19;
	setp.gtu.ftz.f32	%p13, %f20, 0f00000000;
	@%p13 bra 	BB0_12;

	mov.f32 	%f116, 0f00000000;
	bra.uni 	BB0_13;

BB0_12:
	lg2.approx.ftz.f32 	%f83, %f20;
	mul.ftz.f32 	%f84, %f83, 0f3E232000;
	ex2.approx.ftz.f32 	%f116, %f84;

BB0_13:
	setp.gtu.ftz.f32	%p14, %f21, 0f00000000;
	@%p14 bra 	BB0_15;

	mov.f32 	%f117, 0f00000000;
	bra.uni 	BB0_16;

BB0_15:
	lg2.approx.ftz.f32 	%f86, %f21;
	mul.ftz.f32 	%f87, %f86, 0f3E232000;
	ex2.approx.ftz.f32 	%f117, %f87;

BB0_16:
	setp.gtu.ftz.f32	%p15, %f22, 0f00000000;
	@%p15 bra 	BB0_18;

	mov.f32 	%f118, 0f00000000;
	bra.uni 	BB0_19;

BB0_18:
	lg2.approx.ftz.f32 	%f89, %f22;
	mul.ftz.f32 	%f90, %f89, 0f3E232000;
	ex2.approx.ftz.f32 	%f118, %f90;

BB0_19:
	fma.rn.ftz.f32 	%f91, %f116, 0f4196D000, 0f3F560000;
	fma.rn.ftz.f32 	%f92, %f117, 0f4196D000, 0f3F560000;
	fma.rn.ftz.f32 	%f93, %f118, 0f4196D000, 0f3F560000;
	fma.rn.ftz.f32 	%f94, %f116, 0f41958000, 0f3F800000;
	mov.f32 	%f95, 0f3F800000;
	fma.rn.ftz.f32 	%f96, %f117, 0f41958000, 0f3F800000;
	fma.rn.ftz.f32 	%f97, %f118, 0f41958000, 0f3F800000;
	div.rn.ftz.f32 	%f98, %f95, %f94;
	div.rn.ftz.f32 	%f99, %f95, %f96;
	div.rn.ftz.f32 	%f100, %f95, %f97;
	mul.ftz.f32 	%f29, %f91, %f98;
	mul.ftz.f32 	%f30, %f92, %f99;
	mul.ftz.f32 	%f31, %f93, %f100;
	setp.gtu.ftz.f32	%p16, %f29, 0f00000000;
	@%p16 bra 	BB0_21;

	mov.f32 	%f119, 0f00000000;
	bra.uni 	BB0_22;

BB0_21:
	lg2.approx.ftz.f32 	%f102, %f29;
	mul.ftz.f32 	%f103, %f102, 0f429DB000;
	ex2.approx.ftz.f32 	%f119, %f103;

BB0_22:
	setp.gtu.ftz.f32	%p17, %f30, 0f00000000;
	@%p17 bra 	BB0_24;

	mov.f32 	%f120, 0f00000000;
	bra.uni 	BB0_25;

BB0_24:
	lg2.approx.ftz.f32 	%f105, %f30;
	mul.ftz.f32 	%f106, %f105, 0f429DB000;
	ex2.approx.ftz.f32 	%f120, %f106;

BB0_25:
	setp.gtu.ftz.f32	%p18, %f31, 0f00000000;
	@%p18 bra 	BB0_27;

	mov.f32 	%f121, 0f00000000;
	bra.uni 	BB0_28;

BB0_27:
	lg2.approx.ftz.f32 	%f108, %f31;
	mul.ftz.f32 	%f109, %f108, 0f429DB000;
	ex2.approx.ftz.f32 	%f121, %f109;

BB0_28:
	setp.lt.ftz.f32	%p19, %f17, 0f00000000;
	selp.f32	%f110, 0fBF800000, 0f3F800000, %p19;
	setp.lt.ftz.f32	%p20, %f18, 0f00000000;
	selp.f32	%f111, 0fBF800000, 0f3F800000, %p20;
	setp.lt.ftz.f32	%p21, %f19, 0f00000000;
	selp.f32	%f112, 0fBF800000, 0f3F800000, %p21;
	mul.ftz.f32 	%f38, %f121, %f112;
	mul.ftz.f32 	%f39, %f120, %f111;
	mul.ftz.f32 	%f40, %f119, %f110;
	mad.lo.s32 	%r21, %r2, %r3, %r1;
	cvt.s64.s32	%rd1, %r21;
	setp.eq.s32	%p22, %r4, 0;
	@%p22 bra 	BB0_30;

	cvta.to.global.u64 	%rd4, %rd2;
	shl.b64 	%rd5, %rd1, 4;
	add.s64 	%rd6, %rd4, %rd5;
	st.global.v4.f32 	[%rd6], {%f38, %f39, %f40, %f44};
	bra.uni 	BB0_31;

BB0_30:
	cvta.to.global.u64 	%rd7, %rd2;
	shl.b64 	%rd8, %rd1, 3;
	add.s64 	%rd9, %rd7, %rd8;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f40;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f39;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f38;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f44;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd9], {%rs3, %rs2, %rs1, %rs4};

BB0_31:
	ret;
}


